Intel(R) Threading Building Blocks Doxygen Documentation version 4.2.3
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linux_ia32.h
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1/*
2 Copyright (c) 2005-2020 Intel Corporation
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17#if !defined(__TBB_machine_H) || defined(__TBB_machine_linux_ia32_H)
18#error Do not #include this internal file directly; use public TBB headers instead.
19#endif
20
21#define __TBB_machine_linux_ia32_H
22
23#include <stdint.h>
24#include "gcc_ia32_common.h"
25
26#define __TBB_WORDSIZE 4
27#define __TBB_ENDIANNESS __TBB_ENDIAN_LITTLE
28
29#define __TBB_compiler_fence() __asm__ __volatile__("": : :"memory")
30#define __TBB_control_consistency_helper() __TBB_compiler_fence()
31#define __TBB_acquire_consistency_helper() __TBB_compiler_fence()
32#define __TBB_release_consistency_helper() __TBB_compiler_fence()
33#define __TBB_full_memory_fence() __asm__ __volatile__("mfence": : :"memory")
34
35#if __TBB_ICC_ASM_VOLATILE_BROKEN
36#define __TBB_VOLATILE
37#else
38#define __TBB_VOLATILE volatile
39#endif
40
41#define __TBB_MACHINE_DEFINE_ATOMICS(S,T,X,R) \
42static inline T __TBB_machine_cmpswp##S (volatile void *ptr, T value, T comparand ) \
43{ \
44 T result; \
45 \
46 __asm__ __volatile__("lock\ncmpxchg" X " %2,%1" \
47 : "=a"(result), "=m"(*(__TBB_VOLATILE T*)ptr) \
48 : "q"(value), "0"(comparand), "m"(*(__TBB_VOLATILE T*)ptr) \
49 : "memory"); \
50 return result; \
51} \
52 \
53static inline T __TBB_machine_fetchadd##S(volatile void *ptr, T addend) \
54{ \
55 T result; \
56 __asm__ __volatile__("lock\nxadd" X " %0,%1" \
57 : R (result), "=m"(*(__TBB_VOLATILE T*)ptr) \
58 : "0"(addend), "m"(*(__TBB_VOLATILE T*)ptr) \
59 : "memory"); \
60 return result; \
61} \
62 \
63static inline T __TBB_machine_fetchstore##S(volatile void *ptr, T value) \
64{ \
65 T result; \
66 __asm__ __volatile__("lock\nxchg" X " %0,%1" \
67 : R (result), "=m"(*(__TBB_VOLATILE T*)ptr) \
68 : "0"(value), "m"(*(__TBB_VOLATILE T*)ptr) \
69 : "memory"); \
70 return result; \
71} \
72
73__TBB_MACHINE_DEFINE_ATOMICS(1,int8_t,"","=q")
74__TBB_MACHINE_DEFINE_ATOMICS(2,int16_t,"","=r")
75__TBB_MACHINE_DEFINE_ATOMICS(4,int32_t,"l","=r")
76
77#if __INTEL_COMPILER
78#pragma warning( push )
79// reference to EBX in a function requiring stack alignment
80#pragma warning( disable: 998 )
81#endif
82
83#if __TBB_GCC_CAS8_BUILTIN_INLINING_BROKEN
84#define __TBB_IA32_CAS8_NOINLINE __attribute__ ((noinline))
85#else
86#define __TBB_IA32_CAS8_NOINLINE
87#endif
88
89static inline __TBB_IA32_CAS8_NOINLINE int64_t __TBB_machine_cmpswp8 (volatile void *ptr, int64_t value, int64_t comparand ) {
90//TODO: remove the extra part of condition once __TBB_GCC_BUILTIN_ATOMICS_PRESENT is lowered to gcc version 4.1.2
91#if (__TBB_GCC_BUILTIN_ATOMICS_PRESENT || (__TBB_GCC_VERSION >= 40102)) && !__TBB_GCC_64BIT_ATOMIC_BUILTINS_BROKEN
92 return __sync_val_compare_and_swap( reinterpret_cast<volatile int64_t*>(ptr), comparand, value );
93#else /* !__TBB_GCC_BUILTIN_ATOMICS_PRESENT */
94 //TODO: look like ICC 13.0 has some issues with this code, investigate it more deeply
95 int64_t result;
96 union {
97 int64_t i64;
98 int32_t i32[2];
99 };
100 i64 = value;
101#if __PIC__
102 /* compiling position-independent code */
103 // EBX register preserved for compliance with position-independent code rules on IA32
104 int32_t tmp;
105 __asm__ __volatile__ (
106 "movl %%ebx,%2\n\t"
107 "movl %5,%%ebx\n\t"
108#if __GNUC__==3
109 "lock\n\t cmpxchg8b %1\n\t"
110#else
111 "lock\n\t cmpxchg8b (%3)\n\t"
112#endif
113 "movl %2,%%ebx"
114 : "=A"(result)
115 , "=m"(*(__TBB_VOLATILE int64_t *)ptr)
116 , "=m"(tmp)
117#if __GNUC__==3
118 : "m"(*(__TBB_VOLATILE int64_t *)ptr)
119#else
120 : "SD"(ptr)
121#endif
122 , "0"(comparand)
123 , "m"(i32[0]), "c"(i32[1])
124 : "memory"
125#if __INTEL_COMPILER
126 ,"ebx"
127#endif
128 );
129#else /* !__PIC__ */
130 __asm__ __volatile__ (
131 "lock\n\t cmpxchg8b %1\n\t"
132 : "=A"(result), "=m"(*(__TBB_VOLATILE int64_t *)ptr)
133 : "m"(*(__TBB_VOLATILE int64_t *)ptr)
134 , "0"(comparand)
135 , "b"(i32[0]), "c"(i32[1])
136 : "memory"
137 );
138#endif /* __PIC__ */
139 return result;
140#endif /* !__TBB_GCC_BUILTIN_ATOMICS_PRESENT */
141}
142
143#undef __TBB_IA32_CAS8_NOINLINE
144
145#if __INTEL_COMPILER
146#pragma warning( pop )
147#endif // warning 998 is back
148
149static inline void __TBB_machine_or( volatile void *ptr, uint32_t addend ) {
150 __asm__ __volatile__("lock\norl %1,%0" : "=m"(*(__TBB_VOLATILE uint32_t *)ptr) : "r"(addend), "m"(*(__TBB_VOLATILE uint32_t *)ptr) : "memory");
151}
152
153static inline void __TBB_machine_and( volatile void *ptr, uint32_t addend ) {
154 __asm__ __volatile__("lock\nandl %1,%0" : "=m"(*(__TBB_VOLATILE uint32_t *)ptr) : "r"(addend), "m"(*(__TBB_VOLATILE uint32_t *)ptr) : "memory");
155}
156
157//TODO: Check if it possible and profitable for IA-32 architecture on (Linux* and Windows*)
158//to use of 64-bit load/store via floating point registers together with full fence
159//for sequentially consistent load/store, instead of CAS.
160
161#if __clang__
162#define __TBB_fildq "fildll"
163#define __TBB_fistpq "fistpll"
164#else
165#define __TBB_fildq "fildq"
166#define __TBB_fistpq "fistpq"
167#endif
168
169static inline int64_t __TBB_machine_aligned_load8 (const volatile void *ptr) {
170 __TBB_ASSERT(tbb::internal::is_aligned(ptr,8),"__TBB_machine_aligned_load8 should be used with 8 byte aligned locations only \n");
171 int64_t result;
172 __asm__ __volatile__ ( __TBB_fildq " %1\n\t"
173 __TBB_fistpq " %0" : "=m"(result) : "m"(*(const __TBB_VOLATILE uint64_t*)ptr) : "memory" );
174 return result;
175}
176
177static inline void __TBB_machine_aligned_store8 (volatile void *ptr, int64_t value ) {
178 __TBB_ASSERT(tbb::internal::is_aligned(ptr,8),"__TBB_machine_aligned_store8 should be used with 8 byte aligned locations only \n");
179 // Aligned store
180 __asm__ __volatile__ ( __TBB_fildq " %1\n\t"
181 __TBB_fistpq " %0" : "=m"(*(__TBB_VOLATILE int64_t*)ptr) : "m"(value) : "memory" );
182}
183
184static inline int64_t __TBB_machine_load8 (const volatile void *ptr) {
185#if __TBB_FORCE_64BIT_ALIGNMENT_BROKEN
186 if( tbb::internal::is_aligned(ptr,8)) {
187#endif
188 return __TBB_machine_aligned_load8(ptr);
189#if __TBB_FORCE_64BIT_ALIGNMENT_BROKEN
190 } else {
191 // Unaligned load
192 return __TBB_machine_cmpswp8(const_cast<void*>(ptr),0,0);
193 }
194#endif
195}
196
198
199extern "C" void __TBB_machine_store8_slow( volatile void *ptr, int64_t value );
200extern "C" void __TBB_machine_store8_slow_perf_warning( volatile void *ptr );
201
202static inline void __TBB_machine_store8(volatile void *ptr, int64_t value) {
203#if __TBB_FORCE_64BIT_ALIGNMENT_BROKEN
204 if( tbb::internal::is_aligned(ptr,8)) {
205#endif
207#if __TBB_FORCE_64BIT_ALIGNMENT_BROKEN
208 } else {
209 // Unaligned store
210#if TBB_USE_PERFORMANCE_WARNINGS
212#endif /* TBB_USE_PERFORMANCE_WARNINGS */
214 }
215#endif
216}
217
218// Machine specific atomic operations
219#define __TBB_AtomicOR(P,V) __TBB_machine_or(P,V)
220#define __TBB_AtomicAND(P,V) __TBB_machine_and(P,V)
221
222#define __TBB_USE_GENERIC_DWORD_FETCH_ADD 1
223#define __TBB_USE_GENERIC_DWORD_FETCH_STORE 1
224#define __TBB_USE_FETCHSTORE_AS_FULL_FENCED_STORE 1
225#define __TBB_USE_GENERIC_HALF_FENCED_LOAD_STORE 1
226#define __TBB_USE_GENERIC_RELAXED_LOAD_STORE 1
227#define __TBB_USE_GENERIC_SEQUENTIAL_CONSISTENCY_LOAD_STORE 1
228
#define __TBB_machine_cmpswp8
Definition: ibm_aix51.h:42
void __TBB_machine_store8_slow(volatile void *ptr, int64_t value)
Handles misaligned 8-byte store.
void __TBB_machine_store8_slow_perf_warning(volatile void *ptr)
static int64_t __TBB_machine_load8(const volatile void *ptr)
Definition: linux_ia32.h:184
static void __TBB_machine_store8(volatile void *ptr, int64_t value)
Definition: linux_ia32.h:202
static void __TBB_machine_and(volatile void *ptr, uint32_t addend)
Definition: linux_ia32.h:153
static void __TBB_machine_or(volatile void *ptr, uint32_t addend)
Definition: linux_ia32.h:149
static int64_t __TBB_machine_aligned_load8(const volatile void *ptr)
Definition: linux_ia32.h:169
static void __TBB_machine_aligned_store8(volatile void *ptr, int64_t value)
Definition: linux_ia32.h:177
#define __TBB_VOLATILE
Definition: linux_ia32.h:38
#define __TBB_IA32_CAS8_NOINLINE
Definition: linux_ia32.h:86
#define __TBB_fildq
Definition: linux_ia32.h:165
#define __TBB_fistpq
Definition: linux_ia32.h:166
#define __TBB_MACHINE_DEFINE_ATOMICS(S, T, X, R)
Definition: linux_ia32.h:41
#define __TBB_ASSERT(predicate, comment)
No-op version of __TBB_ASSERT.
Definition: tbb_stddef.h:165
void const char const char int ITT_FORMAT __itt_group_sync x void const char ITT_FORMAT __itt_group_sync s void ITT_FORMAT __itt_group_sync p void ITT_FORMAT p void ITT_FORMAT p no args __itt_suppress_mode_t unsigned int void size_t ITT_FORMAT d void ITT_FORMAT p void ITT_FORMAT p __itt_model_site __itt_model_site_instance ITT_FORMAT p __itt_model_task __itt_model_task_instance ITT_FORMAT p void ITT_FORMAT p void ITT_FORMAT p void size_t ITT_FORMAT d void ITT_FORMAT p const wchar_t ITT_FORMAT s const char ITT_FORMAT s const char ITT_FORMAT s const char ITT_FORMAT s no args void ITT_FORMAT p size_t ITT_FORMAT d no args const wchar_t const wchar_t ITT_FORMAT s __itt_heap_function void size_t int ITT_FORMAT d __itt_heap_function void ITT_FORMAT p __itt_heap_function void void size_t int ITT_FORMAT d no args no args unsigned int ITT_FORMAT u const __itt_domain __itt_id ITT_FORMAT lu const __itt_domain __itt_id __itt_id __itt_string_handle ITT_FORMAT p const __itt_domain __itt_id ITT_FORMAT p const __itt_domain __itt_id __itt_timestamp __itt_timestamp ITT_FORMAT lu const __itt_domain __itt_id __itt_id __itt_string_handle ITT_FORMAT p const __itt_domain ITT_FORMAT p const __itt_domain __itt_string_handle unsigned long long value
bool is_aligned(T *pointer, uintptr_t alignment)
A function to check if passed in pointer is aligned on a specific border.
Definition: tbb_stddef.h:370

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